Western Digital: Chief Engineer & Architect, MRAM — San Jose, CA, United States

About Western Digital

Western Digital develops and manufactures data-storage technology for data centres, cloud platforms and enterprise infrastructure. Its employer introduction connects this work with the need to retain, manage and access information generated by digital systems and AI applications. The business brings engineering and manufacturing together around the physical systems behind data storage. Its described purpose is to make growing volumes of information available over time, supporting the infrastructure on which other digital services depend.

The position and its setting

Western Digital lists Chief Engineer & Architect, MRAM in San Jose, CA, United States, under reference REF34885V. The details below separate the work described by the employer from essential conditions, preferred experience and practical preparation advice.

• Employment type: Full-time
• Employer listing date: 23 October 2026
• Business Function: R&D Engineering
• Brands: Western Digital
• Work Location: San Jose Great Oaks Headquarters

Responsibilities and work described

• This role is the most senior technical individual contributor in memory design
• Owns end-to-end product architecture from concept through silicon qualification, arbitrates the power/performance/area trade-offs that set competitiveness, and is the final technical authority across design, process and product engineering
• Define the memory subsystem architecture (array, periphery, I/O, redundancy, test, reliability) and turn product requirements into a design spec
• Drive floorplan and physical architecture: array efficiency, periphery partitioning, power delivery, die-level signal integrity
• Own the multi-generation roadmap: node migration, density and performance scaling
• Decide cross-functional trade-offs across process integration, circuits, DFT, packaging and controller/firmware interfaces
• Own design methodology and EDA/CAD strategy: tools, flows, vendors, licenses
• Mentor senior and principal engineers through architecture and design reviews
• Represent the architecture to executives, customers, foundry partners and standards bodies

Essential requirements and candidate background

• Required
• MS/PhD in EE, CE or related field
• 15+ years in memory or mixed-signal IC development; 5+ as architect or chief engineer
• 2+ memory products owned from architecture through production silicon
• Deep advanced CMOS FinFET expertise: layout, variability, reliability, DFM
• Memory architecture breadth (DRAM, NAND/NOR, SRAM, emerging NVM), depth in one
• Modern Cadence/Synopsys custom and digital flows through full-chip sign-off
• Owned EDA/CAD strategy; led multi-site programs through influence

Preferred experience and additional strengths

• Embedded memory IP integration into SoCs; memory-controller co-design
• Foundry engagement on PDKs, test chips and DTCO
• Emerging NVM architecture
• JEDEC, patents or publications

Location, schedule and contract conditions

For this overseas or regional listing, confirm work authorisation and any location restrictions with the employer. The location does not establish visa sponsorship or permission to work remotely from India.

• Work arrangement: On-site
• Advertised location: San Jose, CA, United States

Benefits mentioned by the employer

• The salary range is what we believe to be the range of possible compensation for this role at the time of this posting
• This range may be modified in the future
• If your position is non-exempt, you are eligible for overtime pay pursuant to company policy and applicable laws
• You may also be eligible for shift differential pay, depending on the shift to which you are assigned
• You may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan
• Please note that not all roles are eligible to participate in the LTI program, and not all roles are eligible for equity under the LTI plan
• RSU awards are also available to eligible new hires, subject to WD's Standard Terms and Conditions for Restricted Stock Unit Awards
• Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable
• Notice To Candidates: Please be aware that WD and its subsidiaries will never request payment as a condition for applying for a position or receiving an offer of employment
• Should you encounter any such requests, please report it immediately to WD Ethics Helpline or email [email protected]

Pay and application dates

A verified salary figure is not established in this article. An online estimate for another Chief Engineer & Architect, MRAM vacancy is not an offer for reference REF34885V; use the employer’s own pay disclosure and recruitment communication.

A closing date is not confirmed in this article. Check the current employer page before submitting: an undated posting can change or be withdrawn.

How to apply to Western Digital

Applications follow the official employer page linked below. The source includes these application-specific points:

Open the official Western Digital posting below and match the title and reference REF34885V.

Compare your qualifications and experience with the essential conditions for the San Jose, CA, United States position, then read the preferred criteria separately.

Prepare an accurate CV and the supporting items requested in that employer’s application. Provide only information and documents you are authorised to share.

Use the employer’s application option, complete the required fields and review the submission. Retain the acknowledgement when one is provided. Job Alerts World does not receive the application.

• Accommodation requests: [email protected]

Practical preparation: firmware

For firmware work, describe the target, the behaviour being implemented and how it was tested on the relevant hardware. Interfaces, timing and debugging methods can help make the contribution concrete.

Relevant skills

• firmware
• CAD
• embedded systems