Renesas Electronics: Senior Staff Engineer, Layout Design (Power & Analog ICs) — Bengaluru, KA, India

About Renesas Electronics

Renesas Electronics develops semiconductors for automotive, industrial, infrastructure and connected-device applications. Its employer description identifies microcontrollers, system-on-chip devices, analogue components and power products within its portfolio. These components form part of electronic systems made by other manufacturers. Renesas also describes combining complementary products into solutions for customers, connecting individual chips with the needs of an end application. Its business therefore involves both semiconductor technology and how that technology is used in wider electronic products.

The position and its setting

Renesas Electronics lists Senior Staff Engineer, Layout Design (Power & Analog ICs) in Bengaluru, KA, India, under reference 20033519_2026-09-14. The details below separate the work described by the employer from essential conditions, preferred experience and practical preparation advice.

• Employment type: Full-time
• Employer listing date: 16 September 2026
• Brands: Renesas Electronics

Responsibilities and work described

• We are seeking a Senior Staff Layout Design Engineer with deep expertise in analog and mixed-signal layout for power and analog IC products
• This is a senior individual-contributor role requiring technical ownership, independent judgment, and the ability to lead layout execution for complex blocks and full-chip designs
• Translate circuit requirements into robust, manufacturable layouts for products such as PMICs, linear and switching regulators, gate drivers, battery-management ICs, and other power and analog devices
• The role requires close collaboration with analog designers, CAD, process, package, reliability, and verification teams
• Be expected to own challenging layout problems, establish best practices, improve methodology and automation, mentor engineers, and drive projects from floor planning through physical verification and tape-out readiness
• Layout Architecture & Execution
• Own floor planning and physical implementation for complex analog, power, and mixed-signal blocks, and contribute to full-chip layout planning
• Collaboration: with circuit designers to capture electrical, matching, isolation, current-density, thermal, reliability, and area requirements
• Apply advanced layout techniques for device matching, parasitic reduction, noise isolation, high-current routing, electromigration robustness, thermal behavior, and yield optimization
• Drive routing, integration, and sign-off readiness for block-level and chip-level layouts
• Physical Verification & Sign-off
• Own and review DRC, LVS, ERC, PEX, antenna, density, latch-up, and reliability verification as required by the process and product
• Analysis: extracted parasitics with designers and support post-layout simulation closure
• Identify physical-design risks early and drive corrective actions with design, CAD, PDK, process, and package teams
• Quality / delivery: layout databases, review records, and release documentation meet tape-out quality standards
• Methodology, Automation & IP Reuse

Essential requirements and candidate background

• Bachelor or Masters degree in Electrical Engineering, Electronics Engineering, or a related discipline
• 10+ years of relevant experience in analog, power, or mixed-signal IC layout and associated development flows
• Demonstrated ownership of complex block-level layout and meaningful contribution to full-chip integration and tape-out
• Deep understanding of matching, parasitic control, noise isolation, guard rings, latch-up prevention, high-current routing, electromigration, IR drop, thermal effects, and reliability-aware layout
• Hands-on expertise with Cadence Virtuoso and physical verification tools such as Calibre, PVS, or equivalent
• Experience: extraction and reliability tools is expected
• Experience working with deep-submicron CMOS and preferably BCD or high-voltage process technologies
• Automate layout or verification tasks using SKILL, TCL, Python, Perl, or similar scripting languages
• Ability to lead technical reviews, mentor engineers, and drive layout methodology improvements
• Cross-functional communication skills in a multisite and multicultural environment
• Results-oriented, self-driven, and able to deliver high-quality work under tight schedules with limited supervision

Location, schedule and contract conditions

• Work arrangement: On-site
• Advertised location: Bengaluru, KA, India

Pay and application dates

A verified salary figure is not established in this article. An online estimate for another Senior Staff Engineer, Layout Design (Power & Analog ICs) vacancy is not an offer for reference 20033519_2026-09-14; use the employer’s own pay disclosure and recruitment communication.

A closing date is not confirmed in this article. Check the current employer page before submitting: an undated posting can change or be withdrawn.

How to apply to Renesas Electronics

Applications follow the official employer page linked below.

Open the official Renesas Electronics posting below and match the title and reference 20033519_2026-09-14.

Compare your qualifications and experience with the essential conditions for the Bengaluru, KA, India position, then read the preferred criteria separately.

Prepare an accurate CV and the supporting items requested in that employer’s application. Provide only information and documents you are authorised to share.

Use the employer’s application option, complete the required fields and review the submission. Retain the acknowledgement when one is provided. Job Alerts World does not receive the application.

Practical preparation: Python

Python work is easier to assess through a concrete example than a list of libraries. Explain the problem, the input data, the parts you implemented and how you checked the output. Include a repository or a short technical note when you can share it.

Relevant skills

• Python
• ISO
• CAD
• electrical engineering
• communication